|Article title||INTEGRATED VLSI FRAGMENT PLACEMENT ALGORITHM|
|Authors||V.V. Kureichik, Vl.Vl. Kureichik|
|Section||SECTION II. AUTOMATION OF DESIGNING|
|Month, Year||07, 2014 @en|
|Abstract||One of the important tasks of the design engineering such as VLSI placement problem is presented in this article. It belongs to the class of NP-hard problem. The paper contains formulation of the placement problem. The models represent the problem of locating and proved multilevel hierarchical decomposition structure. Formulated heuristics, allowing to allocate associated fragments of a graph model of a circuit diagram in the form of building blocks formed by short chains. It was suggested a combined search, implemented by a hierarchical principle on the basis of genetic, evolutionary and algorithms modeling decision-making mechanisms in natural systems. It was developed an integrated algorithm that allows to parallelize the process of solving the problem and partly to eliminate preliminary convergence. Computational experiment was performed. Carried out a series of tests and experiments allowed to specify the theoretical estimation of the time complexity of algorithms and organize their behavior for circuits with different structures. In the best case time complexity of algorithms is about O (nlogn), in the worst case – O (n3).|
|Keywords||Combined search; design engineering; ant algorithm; placement; genetic algorithm.|
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