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Article title A SURVEY ON EFFICIENCY OF MODULAR COMPUTING STRUCTURES FOR SINGLE-CYCLE HARDWARE MULTIPLIER DESIGN
Authors V.M. Amerbaev, R.A. Solovyev, D.V. Telpukhov, A.N. Schelokov
Section SECTION VI. COMPUTER COMPLEXES OF NEW GENERATION AND NEUROCOMPUTERS
Month, Year 07, 2014 @en
Index UDC 004.272.2
DOI
Abstract Methods for constructing modular computing structures based on special moduli sets are presented in this paper. Efficiency comparison of the proposed computational structures was carried out on single-cycle multipliers design, as a typical task for digital signal processing, that is a prior field for residue number systems application. Implementation features of modular and non-modular units, as well as error detection principles for modular structures were considered. Traditional three moduli set {2n-1, 2n, 2n+1} and perspective four moduli set {2k-1, 2k+1, 2k+1-1, 2k+1+1} serve as a basis for considered residue number system structures. IP core generator for functional Verilog descriptions for the multipliers based on these approaches, including traditional binary implementation was designed. With the help of modern CAD Synopsys Design Compiler in the standard cell library basis of 45nm. hardware and time costs estimates were obtained in the range of 3 to 64 input data bits.

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Keywords Modular computing structures; modular multipliers; special moduli sets; modular operations; non-modular operations; residue number system.
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