Article

Article title ABOUT ONE METHOD ACCOUNT OF TEMPORARY DELAY ESTIMATION
Authors A.A. Lezhebokov
Section SECTION II. AUTOMATION OF DESIGNING
Month, Year 09, 2008 @en
Index UDC 683(03)
DOI
Abstract In work the technique of temporary delay estimation arising on interconnections of a circuit is examined at the decision of a NP-difficult task for placement elements in a lattice. In a basis idea the technique of construction model circuit lays on the basis of a Steiner-tree in the orthogonal metrics and temporary delay estimation on each site of a circuit. The available models used for account of delays analysed. The step-by-step procedure for account of an estimation of a temporary delay is offered. The experimental researches have shown sufficient accuracy of offered model and efficiency of application in genetic algorithms as criterion function.

Download PDF

Keywords timing placement, NP-task, VLSI, Elmore model, Steiner tree, genetic algorithms.
References 1. Adya S.N., Yildiz M., Markov I.L., Villarrubia P.G., Parakh P.N., Madden P.H. Benchmarking for large-scale placement and beyond. In Proceedings of the International Symposium on Physical Design. ACM, Monterey, 2003
2. Shervani N. Algorithms for VLSI physical design automation. – USA, Kluwer Academy Pulisher, 1995. – p. 538.
3. Ginneken L.P. Buffer placement in distributed RC-tree networks for minimal Elmore delay // In Proc. IEEE Int. Symp. on Circuits and Systems. 1990. – p. 865-868.
4. Cong J., He L., Koh C. and Pan Z. Global interconnect sizing and spacing with consideration of coupling capacitance // In Proc. Int. Conf. on Computer Aided Design. 1997. – p. 570-573.
5. Cong J., Koh C. and Leung K. Simultaneous buffer and wire sizing for performance and power optimization // In Proc. Int. Symp. on Low Power Electronics and Design. Aug. 1996. – p. 271-276.
6. Tetsushi Koide, Mitsuhiro Ono, A New Performance Driven Placement Method with the Elmore Delay Model for Row Based VLSIs, 2003.
7. Shantanu Dutt, Huan Ren, Fenghua Yuan and Vishal Suthar, “A Network-Flow Approach to Timing-Driven Incremental Placement for ASICs, ICCAD 2006.

Comments are closed.