|Article title||CREATE THE GRAPH OF RESTRICTION BY A METHOD NAMED LIST OF DEPTHS, FOR PROBLEM OF COMPRESSION|
|Authors||B.K. Lebedev, O.V. Ryabov|
|Section||SECTION II. AUTOMATION OF DESIGNING|
|Month, Year||04, 2008 @en|
|Abstract||This article is considering optimization procedures of compression of topology graph restrictions. The existing methods of create of graphs limitations and they draw-backs are considering. A new, more efficient, algorithm for constructing graph restrictions are proposed.|
|Keywords||compression, topology, graph restrictions, algorithm, efficient.|
|References||1. S.B. Akers, J.M. Geyer and D.L. Roberts IC Mask Layout with a Single Conductor Layer // Proceedings of 7th Design Automation Workshop, pages 7-16,1970.
2. M.Y. Hsueh and D.O. Pederson Computer-Aided Layout of LSI Circuit Building-Block // Ph.D. thesis, University of California at Berkeley, December, 1979.
3. C.W. Carpenter and M. Horowitz, Generating Incremental VLSI Compaction Spacing Constraints, Proceedings of the 24th ACM/IEEE Design Automation Conference, pp. 291-297, IEEE Computer Society Press, June 1987.