|Article title||CMOS CIRCUIT STATIC TIMING ANALYSIS ACCOUNTING FOR DESTABILIZING FACTORS|
|Authors||S.V. Gavrilov, G.A. Pirutina, A.N. Schelokov|
|Section||SECTION II. AUTOMATION OF DESIGNING|
|Month, Year||07, 2013 @en|
|Abstract||Improving the reliability of integrated circuits (ICs) become relevant with each new technology. For level design rule 45–32 nm of VLSI design requires a fundamental change in methodology and in CAD tools, in particular requires to static timing analysis of CMOS circuits considering destabilizing factors such as threshold voltage degradation and Negative Bias Temperature Instability. In this article The proposed methods provide a significant increase in the accuracy of destabilizing factors logic level delay degradation analysis in digital circuits due to detailed analysis of the internal gate structure and the correlation of signals in the.|
|Keywords||Static timing analysis; SP-DAG; IP-block.|
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