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Article title SLEEP TRANSISTORS SWITCH AREA DETERMINATION FOR CMOSLOW POWER CIRCUITS BASED ON POWER GATING METHOD WITH OPERATION SPEED CONTROL
Authors P.S. Volobuev, S.V. Gavrilov, D.I. Ryzhova, A.L. Stempkovsky
Section SECTION III. COMPUTER-AIDED DESIGN
Month, Year 06, 2015 @en
Index UDC 621.3.049.771.14
DOI
Abstract Reduction of static power consumption is becoming a priority task in the integrated circuits design process based on the technology with design rules 90nm and below. Existing CAD tools provide low power consumption based on various circuit solutions, like clock gating, multi-Vth transistors and sleep transistor-based methods (power gating). However, the existing data flow on the basis of library elements do not provide the required control of performance when using such method-based circuit solutions for leakage power reduction. The objective of investigation was appraisal of the standard low-power data flow modification capabilities in order to control the operation speed of CMOS circuits while maintaining low static power consumption. Notice in particular that this article is dedicated to finding solution of sleep transistors area estimation and operating speed control in the data flow of automated low-power circuits and intellectual property block (IP blocks) solutions synthesis based on the power gating method. The satisfaction matter of balancing act between static power consumption and operation speed of CMOS circuits is not mentioned in the paper. It is this feature of proposed sleep transistors area estimation method based on timing windows that permits operation speed control to be realized within the presented data-flow without serious modification. The major part of data can be determined during the static timing analysis of the circuit. The proposed method can be implemented in actual data flow as a part of software system for timing analysis.

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Keywords Intellectual property IP-block; static power consumption; CMOS technology.
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