|Article title||SLEEP TRANSISTORS SWITCH AREA DETERMINATION FOR CMOSLOW POWER CIRCUITS BASED ON POWER GATING METHOD WITH OPERATION SPEED CONTROL|
|Authors||P.S. Volobuev, S.V. Gavrilov, D.I. Ryzhova, A.L. Stempkovsky|
|Section||SECTION III. COMPUTER-AIDED DESIGN|
|Month, Year||06, 2015 @en|
|Abstract||Reduction of static power consumption is becoming a priority task in the integrated circuits design process based on the technology with design rules 90nm and below. Existing CAD tools provide low power consumption based on various circuit solutions, like clock gating, multi-Vth transistors and sleep transistor-based methods (power gating). However, the existing data flow on the basis of library elements do not provide the required control of performance when using such method-based circuit solutions for leakage power reduction. The objective of investigation was appraisal of the standard low-power data flow modification capabilities in order to control the operation speed of CMOS circuits while maintaining low static power consumption. Notice in particular that this article is dedicated to finding solution of sleep transistors area estimation and operating speed control in the data flow of automated low-power circuits and intellectual property block (IP blocks) solutions synthesis based on the power gating method. The satisfaction matter of balancing act between static power consumption and operation speed of CMOS circuits is not mentioned in the paper. It is this feature of proposed sleep transistors area estimation method based on timing windows that permits operation speed control to be realized within the presented data-flow without serious modification. The major part of data can be determined during the static timing analysis of the circuit. The proposed method can be implemented in actual data flow as a part of software system for timing analysis.|
|Keywords||Intellectual property IP-block; static power consumption; CMOS technology.|
|References||1. Chandrakasan A., Sheng S., Brodersen R. Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, 1992, Vol. 27, No. 4, pp. 473-484.
2. Calhoun B., Honore F., Chandrakasan A. Design methodology for fine-grained leakage control in MTCMOS, In Proceedings of the 2003 international symposium on Low power electronics and design. ACM Press, 2003, pp. 104-109.
3. Shi K., Howard D. Challenges in sleep transistor design and implementation in low-power designs, Proc. Of the 3rd annual conference on Design automation, 2006, pp. 113-116.
4. Neema V., Chouhan S., Tokekar S. Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack, IETE Journal of Research, 2010, Vol. 56.
5. Mukhopadhyay S., Raychowdhury A., Roy K., Kim C. H. Leakage Power Analysis and Reduction for Nanoscale Circuits, IEEE Micro, 2006, No. 6 (2), pp. 68-80.
6. Royannez P., MairH. 90nm Low Leakage SoC Design Techniques for Wireless Applications, In IEEE International Solid-State Circuits Conference, 2005.
7. CalhounB.H., Honore F.A., Chandrakasan A. Design methodology for fine-grained leakage control in MTCMOS, In Proceedings of the 2003 international symposium on Low power electronics and design, 2003, pp. 104-109.
8. Gavrilov S.V., Ryzhova D.I. Algoritm otsenki pikovogo toka na logicheskom urovne proektirovaniya na osnove analiza rasprostraneniya logicheskikh korrelyatsiy v skheme [Algorithm for estimating peak current at the logical design level based on the analysis of the distribution of logical correlations in the scheme], Vestnik RGRTU [Vestnik of Ryazan state
radioengineering university], 2015, No. 2, Issue 52, pp. 53-61.
9. Gavrilov S.V., Ryzhova D.I., Stempkovskiy A.L. Problema analiza pikovogo toka pri proektirovanii sverkhbol'shikh integral'nykh skhem na logicheskom urovne i sovremennye metody ee resheniya [The problem of peak current analysis in the design of very large integrated circuits on the logic level, and its modern solutions], Informatsionnye tekhnologii [Information Technologies], 2014, No. 6, pp. 58-63.
10. Gavrilov S.V., Ryzhova D.I., Stempkovskiy A.L. Metody povysheniya tochnosti otsenki pikovogo toka na logicheskom urovne na osnove analiza logicheskikh korrelyatsiy [Methods for increasing accuracy of peak current estimation at the logical level based on logic correlation analysis], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2014, № 7 (156), pp. 66-75.
11. Gavrilov S.V., Ryzhova D.I. Metod otsenki pikovogo toka na logicheskom urovne s uchetom odnovremennogo pereklyucheniya vkhodov [A method of evaluating peak current at the logical level due to simultaneous switching of inputs], Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem – 2014. Sbornik trudov [Problems of development of perspective micro - and nanoelectronic systems – 2014. Proceedings of], under ed. academician of RAS A.L. Stempkovskogo. Moscow: IPPM RAN, 2014. Part I, pp. 37-42.
12. Gavrilov S.V., Ryzhova D.I., Shchelokov A.N. Metody povysheniya tochnosti otsenki pikovogo toka na logicheskom urovne na osnove metoda rezolyutsiy [Methods to improve the accuracy of estimates of peak current on the logic level on the basis of resolutions], Trudy Mezhdunarodnogo kongressa po intellektual'nym sistemam i informatsionnym tekhnologiyam – 2014, «IS&IT’14» [Proceedings of the International Congress on intelligent systems and information technologies – 2014, "IS&IT'14"], pp.102-105.
13. Gavrilov S.V., Ryzhova D.I., Shchelokov A.N. Analiz pikovogo toka na osnove rezul'tatov kharakterizatsii real'nykh bibliotek logicheskikh ventiley (tezisy) [Analysis of peak current based on the results of characterization of real libraries of logic gates (abstract)], Trudy Mezhdunarodnogo kongressa po intellektual'nym sistemam i informatsionnym tekhnologiyam
– 2013. Intellektual'nye SAPR» [Proceedings of the International Congress on intelligent systems and information technology – 2013. Intelligent CAD systems"], pp. 251-252.
14. Gavrilov S.V., Gudkova O.N., Severtsev V.N. Interval'nyy staticheskiy vremennoy analiz KMOP-skhem s uchetom logicheskikh korrelyatsiy [Interval static timing analysis for CMOS circuits considering logical correlations], V Vserossiyskaya nauchno-tekhnicheskaya konferentsiya «Problemy razrabotki perspektivnykh mikroelektronnykh sistem – 2012»: sb. nauchn. tr. [V all-Russian scientific-technical conference "problems of development of per-
spective micro-and nanoelectronic systems – 2012": collection of scientific papers], under ed. A.L. Stempkovskogo. Moscow: IPPM RAN, 2012, pp. 113-118.
15. Ganeshpure K. A Pattern Generation Technique for Maximizing Switching Supply Currents, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, pp. 986-998.
16. Mangassarian H., Najm F. Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, pp.271-284.
17. Goldman R., Bartleson K., Wood T., Melikyan V. Synopsys' Interoperable Process Design Kit, European Workshop on Microelectronics Education, 2010.
18. Synopsys Inc. Synopsys products. Available at: http://www.synopsys.com/.
19. HSPICE User Guide: Simulation and Analysis.
20. Volobuev P.S., Gavrilov S.V., Ryzhova D.I. Metod snizheniya staticheskoy moshchnosti KMOP-skhem na osnove otklyuchayushchikh tranzistorov s kontrolem bystrodeystviya [A method of reducing static power CMOS circuits based on the breaking of the transistors control the speed], Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem – 2014.
Sbornik trudov [Problems of development of perspective micro - and nanoelectronic systems ' 2014 – proceedings of], under ed. academician of RAS A.L. Stempkovskogo. Moscow: IPPM RAN, 2014, Part I, pp. 101-106.