Article

Article title OPTIMIZATION OF CODER CIRCUIT BASED ON THE VARIANT COMMUTATIONS SELECTION WITH ACCOUNT FOR LOGIC CORRELATION BETWEEN THE OUTPUTS OF THE COMBINATIONAL CIRCUIT
Authors S.V. Gavrilov, G.A. Ivanova, A.N. Soloviev, A.L. Stempkovskiy
Section SECTION VI. COMPUTING SYSTEMS OF NEW GENERATION AND NEUROCOMPUTERS
Month, Year 06, 2015 @en
Index UDC 621.3.049.771.14
DOI
Abstract This article is dedicated to research and develop methods for increasing the microelectronic circuits’ noise immunity. The role of improving the reliability and noise immunity of designed devices under the influence of various sources of interference and disruption is increases. At present time, the noise immunity factor in microelectronics is becoming critical condition of reliability and working capacity of the developed electronic equipment. Thus one of the key components are combinational circuits. Therefore, research and development of methods for noise immunity improving of microelectronic combinational circuits is actual problem. The operation of division by the polynomial generator in binary Galois field is proposed to use to ensure the necessary level of noise immunity (error detection with a predetermined degree of multiplicity) for the synthesis of the coder circuit. Optimization of coder circuit is proposed by choosing variant of outputs commutation basic circuit duplicate based on the results of logical correlations analysis.

Download PDF

Keywords Noise tolerance; binary decision diagram (BDD); Galois field.
References 1. Gavrilov S.V., Piryutina G.A., Shchelokov A.N. Staticheskiy vremennoy analiz KMOP-skhem s uchetom destabiliziruyushchikh faktorov [CMOS circuit static timing analysis accounting for destabilizing factors], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2013, No. 7 (144), pp. 65-70.
2. GOST 27.310-95. Nadezhnost' v tekhnike. Analiz vidov, posledstviy i kritichnosti otkazov. Osnovnye polozheniya GOST 27.310-95. Reliability in technique. Analysis of types, consequences and criticality of failures. The main provisions]. Moscow: Izd-vo standartov, 1995, 22 p.
3. RD 134-0139-2005. Apparatura, pribory, ustroystva i oborudovanie kosmicheskikh apparatov. Metody otsenki stoykosti k vozdeystviyu zaryazhennykh chastits kosmicheskogo prostranstva po odinochnym sboyam i otkazam, TsNIImash, 2005 [Apparatus, instruments, devices and equipment of spacecraft. Methods of evaluating the resistance to impact of charged particles of space on single errors and failures, TsNIIMash, 2005], 78 p.
4. Sobolev S.A. Funktsional'nyy metod otsenki sootvetstviya apparatury trebovaniyam po otkazam, vyzvannym OYaCh [A functional method for the assessment of conformity of the equipment requirements failure caused EACH], Voprosy atomnoy nauki i tekhniki [Problems of Atomic Science and Technology], 2013, No. 3, pp. 121-132.
5. Shishkevich A.A. Otsenka pokazateley nadezhnosti vychislitel'nykh ustroystv s trekhkratnym mazhorirovaniem pri otkazakh i sboyakh [Evaluation of reliability parameters of computer devices with majorization in three failures and failures], Izvestiya VUZov. Elektronika [News of Higher Educational Institutions. Electronics], 2013, No. 4, pp. 84-88.
6. Solov'ev A.N., Stempkovskiy A.L., Tel'pukhov D.V., Solov'ev R.A., Myachikov M.V. Modelirovanie vozniknoveniya neispravnostey dlya otsenki nadezhnostnykh kharakteristik logicheskikh skhem [Simulation of malfunctions to assess reliability characteristics of logic circuits], Informatsionnye tekhnologii [Information Technologies], 2014, No. 11, pp. 30-36.
7. Solov'ev A.N., Stempkovskiy A.L. Metody povysheniya otkazoustoychivosti raboty ustroystva upravleniya mikrosistemy za schet vvedeniya strukturnoy izbytochnosti [Methods to improve noise tolerance of the device control Microsystems through the introduction of structural redundancy], Informatsionnye tekhnologii [Information Technologies], 2014, No. 10, pp. 17-22.
8. Bryant R.E. Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, 1986, Vol. 35, No. 8, pp. 677-691.
9. Gavrilov S.V., Glebov A.L. BDD-based circuit level structural optimization for digital CMOS, 1-st Intern. Workshop "Multi-Architecture Low Power Design". Moscow, 1999, pp. 45-49.
10. Gavrilov S.V., Gudkova O.N., Shchelokov A.N. Logiko-vremennoy analiz nanometrovykh skhem na osnove interval'nogo podkhoda [Logic timing nanometer circuits analysis using interval approach], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2012, No. 7 (132), pp. 85-91.
11. Gavrilov S.V., Gudkova O.N., Stempkovskiy A.L. The Analysis of the Performance of Nanometer IP-blocks Based on Interval Simulation, Russian Microelectronics, 2013, Vol.42, No. 7, pp. 396-402.
12. Gavrilov S.V., Piryutina G.A., Shchelokov A.N. Metod interval'nykh otsenok zaderzhek i vykhodnykh frontov bibliotechnykh elementov nanometrovykh KMOP-skhem [The interval delay and transition time estimation method of nanometer CMOS library cells], Izvestiya YuFU.
Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2012, No. 7 (132), pp. 70-76.
13. Gavrilov S.V., Glebov A.L., Stempkovskiy A.L. Metody logicheskogo i logiko-vremennogo analiza tsifrovykh KMOP SBIS [Methods of logical and logical-time analysis of digital CMOS VLSI]. Moscow: Nauka, 2007, 223 p.
14. Gavrilov S.V. Metody analiza logicheskikh korrelyatsiy dlya SAPR tsifrovykh KMOP SBIS [Methods of analysis of logical correlations for CAD digital CMOS VLSI]. Moscow: Tekhnosfera, 2011, 136 p.
15. Gavrilov S.V., Glebov A.L., Soloviev R.A., etc Delay Noise Pessimism Reduction by Logic Correlations, In Proc. of ICCAD, 2004, pp. 160-167.
16. Gavrilov S.V., Ryzhova D.I., Stempkovskiy A.L. Metody povysheniya tochnosti otsenki pikovogo toka na logicheskom urovne na osnove analiza logicheskikh korrelyatsiy [Methods for increasing accuracy of peak current estimation at the logical level based on logic correlation analysis], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya SFedU. Engineering Sciences], 2014, No. 7 (156), pp. 66-75.
17. Gavrilov S.V., Ryzhova D.I. Algoritm otsenki pikovogo toka na logicheskom urovne proektirovaniya na osnove analiza rasprostraneniya logicheskikh korrelyatsiy v scheme [The estimation algorithm of the peak current at the logical design level based on the analysis of the distribution of logic correlations in the circuit], Vestnik Ryazanskogo gosudarstvennogo
radiotekhnicheskogo universiteta [Vestnik of Ryazan State Radio Engineering University], 2015, No. 2 (Issue 52), pp. 53-61.
18. Gavrilov S.V., Gudkova O.N., Severtsev V.N. Interval'nyy staticheskiy vremennoy analiz KMOP-skhem s uchetom logicheskikh korrelyatsiy [Interval static timing analysis for CMOS circuits considering logical correlation], V Vserossiyskaya nauchno-tekhnicheskaya konferentsiya “Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh sistem – 2012”: sb. nauchn. tr. [V all-Russian scientific-technical conference “problems of develop-
ment of perspective micro- and nanoelectronic systems – 2012”: collection of scientific papers], Under the General ed. A.L. Stempkovskogo. Moscow: IPPM RAN, 2012, pp. 113-118.
19. Glebov A.L., Gavrilov S.V., Blaauw D. False-noise analysis using resolution method. ISQED-2002.
20. Stempkovskiy A.L., Gavrilov S.V., Glebov A.L. Analiz pomekhoustoychivosti tsifrovykh skhem na osnove metoda rezolyutsiy [Analysis of noise immunity of digital circuits on the basis of resolutions], Izvestiya VUZov. Elektronika [News of Higher Educational Institutions. Electronics], 2004, No. 6, pp. 64-71.

Comments are closed.