Authors P.S. Poperechny
Month, Year 07, 2015 @en
Index UDC 004.67
Abstract This article proposes a method, based on traditional BCH (Bose–Chaudhuri–Hocquenghem) encoder for implementation with parallel input data processing, and with on-demand adjusting correcting level capability. There is original encoder scheme but with adjustable generating polynomial, stored in the rewritable registers. Also the encoder parallelization structure is proposed in-common for any data bus width. As a result, the parallel adjustable encoder scheme is proposed in-common for any data bus and any polynomial. Here is mathematical equation for parallel encoder implementation with variable error-for-correct number. The equation allows to implement both software and hardware encoder. There is hardware implementation of this correction method. There are details of the proposed implementation, and comparison examples with different input databus width by means of state-of-art FPGA CAD. The proposed encoder has hardware resources benefits due to universality for application in any memory devices. Also due to the parallel input data processing the encoder has better data throughput comparing with traditional encoder. So, the same approach of parallelization can be used in decoding, the syndrome calculation scheme, cause this scheme is very similar to the encoder scheme. In spite of much more complexity of decoding algorithm rather than encoding, an adjustable decoding is implemented simpler. To change the error correction level of decoding needs to vary the clock cycles of the error polynomial locator correspondently.

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Keywords BCH; correcting level capability; linear feedback shift register (LFSR); Galois field.
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