Authors S.A. Shostachenko, R.V. Zakharchenko, S.V. Minnebaev, R.V. Ryzhuk, M.M. Maslov, K.P. Katin, N.I. Kargin, N.G. Kovalchuk, I.V. Komissarov, V.A. Labunov
Month, Year 09, 2015 @en
Index UDC 621.382.3
Abstract In this article we have studied the influence of Si3N4 and SiO2 thin film gate dielectrics on  the current-voltage characteristics of graphene based transistor. Test structure of graphene tran sistor was fabricated with the top and back gate. Graphene has been produced by chemical vapor  deposition, and then transferred to the silicon dioxide on silicon wafer. The channel of the transis tor has been formed by etching in oxygen plasma through a photolithographic mask. Metals elec trodes of drain, source and gate were deposited by resistive evaporation in vacuum. It was used  titanium / aluminum with a thickness of 50/200 nm. In the case of the back gate silicon dioxide was  used, obtained by thermal oxidation of the silicon substrate. For top gate was used silicon nitride  deposited by plasma chemical deposition. It was demonstrated that field effect is more pronounced for the case of SiO2 back gate compare to the Si3N4 top gate. For the SiO2 back gate we have observed that the source- drain current decreases, from 2 mA to 3 mA, with increasing of the gate  voltage, from 0 to 40 V, at constant source-drain voltage, 2 V. In case of Si3N4 top gate the modulation of source drain current was not significant for the comparable electric filed strength. Based  on the value of gate voltage for current minima in transfer function the poor quality of Si3N4 – graphene interface is concluded.

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Keywords Nanotechnology; field-effect transistor; graphene; gate dielectric; silicon nitride; silicon dioxide.
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