Authors S.V. Gavrilov, D.I. Ryzhova, A.L. Stempkovskiy
Month, Year 06, 2016 @en
Index UDC 621.3.049.771.14
Abstract With a decrease in the technological size of the basic elements, the negative impact of short-channel effects in the transistor increases and the electrical transistors parameters of degradation becomes more noticeable. This leads to the development of alternative technical solutions, it can be scaled and it is compatible with CMOS manufacturing process. One of the most perspective approaches in this area is the synthesis of the CMOS circuits layout with three-dimensional transistor gate technology (FinFET, Fin Field Effect Transistor). The advantages of this technology are the low sensitivity to the short-channel effects in the transistor and a low subthreshold leakage. Today the CAD tools for fully automated synthesis of circuit layout based on FinFET structures are absent, as the number of design rules and constraints on technology 22 nm and below is significantly increased. We use regular structures in the lower layers of the layout. It allows us to solve the problem of the increasing number of design rules for 22 nm technology and below. In the Intel company an approach to the design of regular topological structures using a special constraction (so-called transistor pattern) for compliance with the requirements of regularity in the computer-aided desing (CAD) systems is proposed. This work represents a further development of the idea of use the regularity of topological structures in CAD systems for ASIC design. A distinctive feature of the proposed approach is the independent synthesis of pull-up and pull-down chains using nesting graph of series-parallel structures (SP-graph). It provides an additional degree of freedom to achieve desired values of the area, performance and power consumption of circuit compared to standard approaches based on pre-defined library of elements. In this paper, the design automation flow for CMOS technology with 3D structure of the transistor is proposed. This flow allows to obtain the required accuracy of delays and minimize the final layout area.

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Keywords SP-DAG (serial-parallel directed acyclic graph); CAD (computer-aided design); IP-block; FinFET transistor; CMOS technology
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