Article

Article title LOGICAL SENSITIVITY FACTOR ESTIMATION FOR COMBINATIONAL CIRCUITS USING PROBABILISTIC METHODS
Authors D.V. Telpukhov, R.A. Solovyev, N.V. Telpukhova, A.N. Sсhelokov
Section SECTION IV. COMPUTER ENGINEERING AND ELECTRONICS
Month, Year 07, 2016 @en
Index UDC
DOI DOI 10.18522/2311-3103-2016-7-149158
Abstract Modern microelectronic development course is closely associated with the miniaturization of devices and reduction of dimensions in technological process which reduces fault-tolerance and raises questions about ways of designing reliable integrated circuits (IC). In the early stages of IC development when no parameters of the electronic components are defined, it is often required to make preliminary estimates of fault tolerance for the use of various methods of increasing the masking properties of the developed logic. Calculation of precise fault tolerance characteristics, such as fault polynomial requires significant computational resources and cannot be used for medium and large circuits. Consequently, there is a growing need for approximations that take into account this limitation. For such a metrics, we propose the generalized coefficient of logic sensitivity to single faults. This parameter has a linear computational complexity relative to the number of elements and does not depend on the probability of gate failure. Moreover, under the conditions where the probability of gate failure tends to zero – this is the most accurate approximation being a tangent to the curve of the polynomial error at zero. Moreover, the use of methods of probabilistic logic provides additional opportunities to reduce the computation time, obtaining the desired estimate of circuit reliability in linear time in single pass. Experiments have shown the ability to increase the range of applicability of this metric for large combinational circuits with some loss in accuracy.

Download PDF

Keywords Fault-tolerance; combinational circuits; logical masking; the logical sensitivity factor.
References 1. Dodd P.E. et al. Production and propagation of single-event transients in high-speed digital logic ICs, IEEE Transactions on Nuclear Science, 2004, Vol. 51, No. 6, pp. 3278-3284.
2. Benedetto J.M. et al. Digital single event transient trends with technology node scaling, IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, pp. 3462-3465.
3. Chen Y. et al. Radiation hardened by design techniques to mitigating P-hit single event transient, Nanoelectronics Conference (INEC), 2016 IEEE International. IEEE, 2016, pp. 1-2.
4. Costenaro E. et al. A practical approach to single event transient analysis for highly complex design, Journal of Electronic Testing, 2013, Vol. 29, No. 3, pp. 301-315.
5. Stempkovskiy A.L., Tel'pukhov D.V., Solov'ev R.A., Solov'ev A.N., Myachikov M.V. Modeliro-vanie vozniknoveniya neispravnostey dlya otsenki nadezhnostnykh kharakteristik logicheskikh skhem [Simulation of malfunctions to assess the fault tolerance characteristics of log-ic circuits], Informatsionnye tekhnologii [Information Technology], 2014, No. 11, pp. 30-36.
6. J. von Neumann. Probabilistic logics and the synthesis of reliable organisms from unreliable components, in Automata Studies, C.E. Shannon and J. McCarthy, Eds. Princeton, NJ: Prince-ton Univ. Press, 1956, pp. 43-98.
7. Xiao R., Chen C. Gate-level circuit reliability analysis: A survey, VLSI Design, 2014,
Vol. 2014, Article ID 529392, pp. 1-12.
8. Stempkovskiy A.L., Tel'pukhov D.V., Solov'ev R.A., Myachikov M.V. Povyshenie ot-kazoustoychivosti logicheskikh skhem s ispol'zovaniem nestandartnykh mazhoritarnykh ele-mentov [Improving the fault tolerance of logical circuits using majority of non-standard elements], Informatsionnye tekhnologii [Information Technology], 2015, Vol. 21, No. 10, pp. 749-756.
9. Tel'pukhov D.V., Solov'ev R.A., Myachikov M.V. Razrabotka prakticheskikh metrik dlya otsenki metodov povysheniya sboeustoychivosti kombinatsionnykh skhem [Development of practical metrics to evaluate methods to improve the failure tolerance of combina-tional circuits], Informatsionnye tekhnologii i matematicheskoe modelirovanie sistem 2015: Trudy Mezhdunarodnoy nauchno-tekhnicheskoy konferentsii [Information technologies and mathematical system modeling 2015: Proceedings of International scientific-technical conference], 2015, pp. 79-81.
10. Choudhury MR, Mohanram K. Reliability analysis of logic circuits, IEEE Trans CAD, 2009, No. 28 (3), pp. 392-405.
11. Stanisavljević M., Schmid A., Leblebici Y. Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures. Springer Science & Business Media, 2010.
12. Stempkovskiy A.L., Tel'pukhov D.V., Solov'ev R.A., Myachikov M.V., Tel'pukhova N.V. Raz-rabotka tekhnologicheski-nezavisimykh metrik dlya otsenki maskiruyushchikh svoystv logicheskikh skhem [Development of technology-independent metrics for evaluating masking properties of logical schemes], Vychislitel'nye tekhnologii [Computational Technologies], 2016, Vol. 21, No. 2.
13. Han J, Chen H, Boykin E, Fortes J. Reliability evaluation of logic circuits using probabilistic gate models, Microelectronics Reliability, 2011, No. 51 (2), pp. 468-76. 20.
14. Jie Han, Erin Taylor, Jianbo Gao and José Fortes. Faults, Error Bounds and Reliability of Nanoelectronic Circuits. Proceedings of the16th International Conference on Application-Specific Systems, Architecture and Processors (ASAP’05). 1063-6862/05 2005 IEEE 19.
15. Nasir Mohyuddin, Ehsan Pakbaznia and Massoud Pedram. Probabilistic Error Propagation in Logic Circuits Using the Boolean Difference Calculus. University of Southern California De-partment of Electrical Engineering Los Angeles, CA, USA.
16. Choudhury MR, Mohanram K. Reliability analysis of logic circuits, IEEE Trans CAD, 2009, No. 28 (3), pp. 392-405.
17. Mahdavi S.J. Seyyed, Mohammadi K. Improved single-pass approach for reliability analysis of digital combinational circuits, Microelectronics Reliability, 2011, No. 51, pp. 477-484.
18. Milos Stanisavljevic, Alexandre Schmid and Yusuf Leblebici. Output Probability Density Func-tions of Logic Circuits: Modeling and Fault-Tolerance Evaluation. Microelectronic Systems Laboratory, EPFL, CH-1015 Lausanne, Switzerland. 978-1-4244-6471-5/10/$26.00c 2010 IEEE.
19. Pilgrim M., Willison S. Dive Into Python 3. Apress, 2009, Т. 2.
20. Brezinski C., Zaglia M.R. Extrapolation methods: theory and practice. Elsevier, 2013, Т. 2.

Comments are closed.