Authors D.V. Telpukhov, R.A. Solovyev, N.V. Telpukhova, A.N. Sсhelokov
Month, Year 07, 2016 @en
Index UDC
DOI DOI 10.18522/2311-3103-2016-7-149158
Abstract Modern microelectronic development course is closely associated with the miniaturization of devices and reduction of dimensions in technological process which reduces fault-tolerance and raises questions about ways of designing reliable integrated circuits (IC). In the early stages of IC development when no parameters of the electronic components are defined, it is often required to make preliminary estimates of fault tolerance for the use of various methods of increasing the masking properties of the developed logic. Calculation of precise fault tolerance characteristics, such as fault polynomial requires significant computational resources and cannot be used for medium and large circuits. Consequently, there is a growing need for approximations that take into account this limitation. For such a metrics, we propose the generalized coefficient of logic sensitivity to single faults. This parameter has a linear computational complexity relative to the number of elements and does not depend on the probability of gate failure. Moreover, under the conditions where the probability of gate failure tends to zero – this is the most accurate approximation being a tangent to the curve of the polynomial error at zero. Moreover, the use of methods of probabilistic logic provides additional opportunities to reduce the computation time, obtaining the desired estimate of circuit reliability in linear time in single pass. Experiments have shown the ability to increase the range of applicability of this metric for large combinational circuits with some loss in accuracy.

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Keywords Fault-tolerance; combinational circuits; logical masking; the logical sensitivity factor.
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