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Article title METHODOLOGY OF IMPLEMENTATION OF LARGE NODES OF COMPUTATIONAL PROBLEMS AS LIBRARY VHDL-UNITS ON RECONFIGURABLE COMPUTER SYSTEMS
Authors Yu.I. Doronchenko, A.G. Kovalenko
Section SECTION I. PRINCIPLES OF THE ARCHITECTURE OF SUPERCOMPUTERS
Month, Year 11, 2016 @en
Index UDC 004.315
DOI 10.18522/2311-3103-2016-11-413
Abstract The paper covers a methodology of implementation of large computational nodes as library VHDL-units for reconfigurable computer systems. A library of circuit elements for Xilinx UltraScale FPGAs is presented. The library was developed in Scientific Research Centre of Supercomputers and Neurocomputers (Taganrog, Russia). All elements were implemented in the VHDL language. Owing to this they can be used not only for the abovementioned FPGA family but for FPGAs of various vendors and families. The maximal capabilities of the library are given to developers who create applications in the high-level language COLAMO, because use of any element from the library is automatic and depends on the program code. The library of circuit elements is divided into groups according to functions (communication, floating point operations, integer operations, logical operations, data storage, etc.), capacity (variable capacity, 32-digit capacity, 64-digit capacity, other capacities) and presence/absence of triggers in output buses of elements. The total number of groups is 20. The library contains VHDL-descriptions of more than 300 circuit elements. The clock rate of the elements is from 450 to 550 MHz for UltraScale FPGAs. The current structure of circuit elements description is adapted for their use in the development environment using the language COLAMO. VHDL-description of the library elements contains a specialized structure of commentaries for a synthesizer Fire!Constructor, which is a tool of the application development software suit. The methodology, which allows creating a library of large nodes of computational problems for RCS, is described. The developed library of circuit elements can be useful for experienced developers for reduction of the projects development time, and for entry-level circuit engineers and applications developers. It will help them to achieve rather high performance of their solutions without multiple optimizations of code and detailed analysis of FPGA structure, which can be modified, improved and added by the developer depending on the problem domain of soling tasks. Owing to the suggested methodology of implementation of large computational nodes as library VHDL-units it is possible to reduce the implementation time of computationally laborious problems on RCS up to 30 %.

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Keywords Reconfigurable computer structure; FPGA programming; VHDL; programming language COLAMO; library of circuit elements.
References 1. Levin I.I., Dordopulo A.I., Kalyaev I.A., Doronchenko Yu.I., Raskladkin M.K. Sovremennye i perspektivnye vysokoproizvoditel'nye vychislitel'nye sistemy s rekonfiguriruemoy arkhitekturoy [Modern and perspective high performance computer systems with reconfigurable architecture ], Vestnik Yuzhno-Ural'skogo gosudarstvennogo universiteta. Seriya: Vychislitel'naya matematika i informatika [Vestnik of the South Ural state University. Series: Computational mathematics and computer science], 2015, Vol. 4, No. 3, pp. 24-39.
2. Available at: http://www.xilinx.com/products/design-tools/vivado.html (accessed 14 October 2016).
3. Available at: http://www.xilinx.com (accessed 14 October 2016).
4. Bibilo P.N. Osnovy yazyka VHDL [The basics of the language VHDL]. Moscow: SOLON-R, 2002, 224 p.
5. Yazyki vysokogo urovnya ImpulseC, Mitrion-C i Handle-C [High-level languages ImpulseC, Mitrion-C and Handle C]. Available at: https://parallel.ru/fpga/lang.html (accessed 14 October 2016).
6. Available at: http://www.superevm.ru (accessed 14 October 2016).
7. Available at: https://www.xilinx.com/products/silicon-devices/fpga/kintex-ultrascale.html (accessed 14 October 2016).
8. Available at: https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale.html (ac-cessed 14 October 2016).
9. Kalyaev I.A., Levin I.I., Semernikov E.A., Shmoylov V.I. Rekonfiguriruemye mul'tikonveyernye vychislitel'nye struktury [Multiconference reconfigurable computing structure]. 2nd ed., under the ed. I.A. Kalyaeva. Rostov-on-Don: Izd-vo YuNTs RAN, 2009, 344 p.
10. Available at: http://www.mvs.sfedu.ru (accessed 14 October 2016).
11. 754-2008 - IEEE Standard for Floating-Point Arithmetic. Available at: http://ieeexplore.ieee.org/ document/4610935/ (accessed 14 October 2016).
12. Dordopulo A.I. Gudkov V.A., Gulenok. A.A. Programmirovanie mnogokristal'nykh rekonfiguriruemykh vychislitel'nykh sistem na yazykakh vysokogo urovnya Mitrion-C i COLAMO [Programming a multi-chip reconfigurable computing systems high-level language Mitrion-C and COLAMO], Materialy VI mezhdunarodnoy nauchno-prakticheskoy konferentsii «Akademicheskaya nauka – problemy i dostizheniya» 25-26 maya 2015 g. [Materials of VI in-ternational scientific-practical conference "Academic science – problems and achievements" on 25-26 may 2015]. North Charleston, SC, USA,2015, Vol. 1, pp. 122-127.
13. Gudkov V.A., Gulenok A.A., Kovalenko V.B., Slasten L.M. Multi-level Programming of FPGA-based Computer Systems with Reconfigurable Macroobject Architecture, IFAC Proceedings Volumes (ISSN 14746670), Programmable Devices and Embedded Systems 2013 Vol. 12,
part 1, pp. 204-209.
14. Levin I.I., Dordopulo A.I., Gulenok A.A. Sintez parallel'nykh prikladnykh programm dlya mnogokristal'nykh rekonfiguriruemykh vychisliteley. Sintezator Fire!Constructor: ucheb. posobie [Synthesis of parallel programs for multi-chip reconfigurable computers. Synth Fire!Constructor: a training manual]. Taganrog: Izd-vo TTI YuFU, 2013, 96 p.
15. Bovkun A.V., Levin I.I., Dordopulo A.I., Gulenok A.A. Sredstva translyatsii parallel'nykh programm na uroven' logicheskikh yacheek PLIS dlya mnogokristal'nykh rekonfiguriruemykh vychislitel'nykh sistem [Means of translating parallel programs on the level of logical cells of the FPGA for multi-chip reconfigurable computing systems], Trudy Pervogo Mezhdunarodnogo simpoziuma «Gibridnye i sinergeticheskie intellektual'nye sistemy: teoriya i praktika», 29 iyunya-2 iyulya 2012 g., g. Svetlogorsk Kaliningradskaya oblast' [Proceedings of the First International Symposium on "Hybrid and synergetic intelligent systems: theory and practice", June 29-July 2, 2012, Svetlogorsk, Kaliningrad oblast]. Kaliningrad: Izd-vo BFU im. Kanta, 2012, pp. 97-107.
16. Levin I.I., Dordopulo A.I., Gudkov V.A. Programmirovanie rekonfiguriruemykh vychislitel'nykh uzlov na yazyke COLAMO: ucheb. posobie [Programming reconfigurable computational nodes in the language COLAMO: a training manual]. Taganrog: Izd-vo TTI YuFU, 2011, 114 p.
17. Guzik V.F., Kalyaev I.A., Levin I.I. Rekonfiguriruemye vychislitel'nye sistemy: ucheb. posobie [Reconfigurable computing systems: the textbook], ed. by I.A. Kalyaeva. Rostov-on-Don: Izd-vo YuFU, 2016, 472 p.
18. Perel'royzen E.Z. Proektiruem na VHDL [Design in VHDL]. Moscow: SOLON-Press, 2004, 448 p.
19. Maksfild K. Proektirovanie na PLIS. Kurs molodogo boytsa [The design on the FPGA. Course of the young fighter]. Moscow: Izdatel'skiy dom «Dodeka-XXI», 2007, 408 p.
20. Sergienko A.M. VHDL dlya proektirovaniya vychislitel'nykh ustroystv [VHDL for the design of computing devices]. Kiev: ChP «Korneychuk», OOO «TID «DS», 2003, 208 p.

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