Article

Article title MODULAR-LOGARITHMIC PROCESSOR
Authors I.P. Osinin
Section SECTION I. PRINCIPLES OF THE ARCHITECTURE OF SUPERCOMPUTERS
Month, Year 11, 2016 @en
Index UDC 004.272.34
DOI 10.18522/2311-3103-2016-11-1326
Abstract The article describes the organization of perspective modular-logarithmic processor. The key difference from analogues is the use of non-positional number system based on homogeneous computing environments which parallelize computations until operand bits, increasing the speed of calculations, and also has introduced a number of unique properties that significantly improve the reliability of computations. Application of residual classes in conjunction with the logarithmic number system instead of the floating-point allowed us to use a range of the digit representation analogous to IEEE-754 format, while refusing the slow operation of rounding and smoothing or-ders. The current implementation in the form of soft-block IP processor confirms the feasibility of the architectural features which are described in the article. In the future, such a processor can be designed not only as a complement system on a chip, but also as an independent device. For ex-ample, as an arithmetic accelerator connected to the traditional architecture of the computer or as a CPU based on VLSI. In any of these embodiments, the high performance, scalability and reconfigurability are achieved by the use of homogeneous computing environments, operating in the basis of the residual class system and the logarithmic number system. The application areas for MLP are the following: high performance computing, requiring working with large digit data – 1024 bits or more (climate modeling tasks, the study of electromagnetic scattering study of the orbital evolution of celestial bodies and others), where due to paralleling the account on multiple independent residuals achieved growth performance compared to known analogs (such as integers at least twice compared with Intel AVX-512 while reducing the hardware cost by 17 %); highly reliable computing, requiring constant monitoring of correctness of calculations (missile guidance problem, the control of nuclear power plant operation of spacecraft and the like), which through the use of SOC correcting properties achieved is a decrease in hardware costs if to compare to the analogs.

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Keywords Processor; RNS; LNS; reconfigurable architecture; highly reliable computing.
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