Authors A. L. Stempkovskiy, D. V. Telpuhov, T. D. Zhukova, S. I. Gurov, R. A. Solovyev
Month, Year 07, 2017 @en
Index UDC 621.3.049.771.14
Abstract Currently, the urgency of research in the field of improving the reliability of the microelectronic systems is steadily increasing. It happens due to the continuing miniaturization, which leads to a reduction in the threshold of impact, necessary for the occurrence of soft and hard errors. One of the possible solutions to this problem can be the approach related to the correction of errors occurring during the work process. To solve the problem of automatic error correction, arising from the faults in combinational circuits, there is an approach associated with the use of redundant coding. Building a self-checking circuit is the traditional approach for the solution of the problem. Self-correction is provided by creating, in addition to the main functional scheme, a monitoring and detecting one, often resulting in a too long delay in obtaining the result. This direction is very promising and is now the subject of intensive research, but currently there is no clearly formulated principles for designing such schemes. In this article the basic principles of self-correcting schemes based on methods of redundant coding are considered, various error-correcting codes in the field of self-correcting combinational circuits are analyzed, and general recommendations on the use of error-correcting codes with respect to the problem of constructing fault-tolerant combinational circuits are developed. The article also offers a method for synthesizing fault-tolerant CMOS circuits based on Hamming bit spaces. The method consists in replacing the elementary Boolean gates with their fault-tolerant analogs, providing correction of errors on each gate. The proposed method exploits the idea of selective protection at the level of individual gates, but it has significant differences from simple elementwise TMR. We also carried out computational experiments and compared the method with triple modular redundancy for the case of single and multiple failures. Method for synthesizing fault-tolerant CMOS circuits based on Hamming bit spaces demonstrated a high level of failure stability with a significant increase in hardware costs.

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Keywords Fault tolerance; error correction; combinational circuits.
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