|Article title||IP-CORE FOR A FUNCTIONAL-ORIENTED PROCESSOR WITH VLIW-RISC ARCHITECTURE|
|Authors||N. A. Lookin|
|Section||SECTION I. PRINCIPLES OF CONSTRUCTION OF HIGH-PERFORMANCE COMPUTING SYSTEMS|
|Month, Year||08, 2018 @en|
|Index UDC||004.2, 004.31|
|Abstract||The analysis of algorithms of real-time control systems shows that in order to ensure the required performance of embedded computer systems, it is necessary to ensure the minimum time for processing the specific algorithmic procedures. The VLSI implementation of special-purpose architectures of embedded processors allows, due to the hardware implementation of such procedures, to significantly minimize the processing time. The main goals of the synthesis of IP-core of the functional-oriented processor in this case are the maximum possible performance of processing of the basic procedure and a minimum of overhead costs for the programs functioning. The IP-core, based on a combination of RISC architecture and VLIW-class instructions, makes it possible to achieve these goals when computing the scalar product of vectors, adopted as the basic procedure. A high-performance 64-bit processor core has been developed, which performs any operation of the instruction set in no more than one clock cycle, ensuring minimal computing time for the scalar product. This leads to the fastest possible implementation of navigation algorithms for control systems for rocket and space technology and aircraft. The article discusses the results of the development of technological software designed for the design and verification of application programs of a function-oriented processor. The structure of this software includes a specialized assembler language DAPLANG, created on the basis of the ML-1 macro-generator, as well as a special library for interacting FOP with the Lua scripting language. The results of experimental studies of FOP with for verifying the architecture and system of commands are given.|
|Keywords||Functional-oriented processor; IP-core; real-time systems.|
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