Article

Article title THE INTERVAL DELAY AND TRANSITION TIME ESTIMATION METHOD OF NANOMETER CMOS LIBRARY CELLS
Authors S.V. Gavrilov, G.A. Pirutina, A.N. Schelokov
Section SECTION II. AUTOMATION OF DESIGNING
Month, Year 07, 2012 @en
Index UDC 621.3.049.771.14
DOI
Abstract A wide set of digital circuit simulation problems requires both maximal node delay and minimal delay. The accurate minimal delay model depends on glitches and simultaneous gate input switching. But the existing logic level performance analysis tools, as a rule, use simplified pin-to-pin- gate delay model. This paper describes the method, which provides considerable logic level interval delay analysis accuracy versus the famous approaches accounting for the simultaneous multiple input switching.

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Keywords Static timing analysis; gate delay; IP-block.
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