Article

Article title LOGIC TIMING NANOMETER CIRCUITS ANALYSIS USING INTERVAL APPROACH
Authors S.V. Gavrilov, O.N. Gudkova, A.N. Schelokov
Section SECTION II. AUTOMATION OF DESIGNING
Month, Year 07, 2012 @en
Index UDC 621.3.049.771.14
DOI
Abstract This paper is dedicated to IP-blocks performance analysis technique development, which is based on interval simulation accounting for element parameter variations. The traditional performance analysis of test stimulus sequence orders the events during time, while the proposed technique provides space ordering. This technique results in true logic path analysis, combines the high speed of critical path analysis with good accuracy due to accurate delay model.

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Keywords IP-block; logic-timing analysis; SP-DAG; static timing analysis.
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